MAX11101EUB+【PDF 19/19 页】IC ADC 14BIT SRL 200KSPS 10UMAX

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Maxim Integrated Products 9

MAX11101

14-Bit, +5V, 200ksps ADC with 10A Shutdown

Detailed Description

The MAX11101 includes an input track-and-hold (T/H)

and successive-approximation register (SAR) circuitry to

convert an analog input signal to a digital 14-bit output.

Figure 4 shows the MAX11101 in its simplest configura-

tion. The serial interface requires only three digital lines

(SCLK, CS, and DOUT) and provides an easy interface

to microprocessors (FPs).

The MAX11101 has two power modes: normal and shut-

down. Driving CS high places the MAX11101 in shut-

down, reducing the supply current to 0.1FA (typ), while

pulling CS low places the MAX11101 in normal operating

mode. Falling edges on CS initiate conversions that are

driven by SCLK. The conversion result is available at

DOUT in unipolar serial format. The serial data stream

consists of eight zeros followed by the data bits (MSB

first). Figure 3 shows the interface-timing diagram.

Analog Input

Figure 5 illustrates the input sampling architecture of the

ADC. The voltage applied at REF sets the full-scale input

voltage.

Track-and-Hold (T/H)

In track mode, the analog signal is acquired on the inter-

nal hold capacitor. In hold mode, the T/H switches open

and the capacitive DAC samples the analog input.

Figure 1. Load Circuits for DOUT Enable Time and SCLK to

DOUT Delay Time

Figure 2. Load Circuits for DOUT Disable Time

Figure 3. Detailed Serial Interface Timing

DOUT

a) VOL TO VOH

b) HIGH-Z TO VOL AND VOH TO VOL

DOUT

1mA

DGND

CLOAD = 50pF

VDD

DOUT

a) VOH TO HIGH-Z

b) VOL TO HIGH-Z

DOUT

1mA

DGND

CLOAD = 50pF

VDD

SCLK

DOUT

tCSS

tCH

tCL

tDV

tCSH

tCSW

tTR

tDO

tCP

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